The present invention relates generally to semiconductor fabrication and more specifically to methods of forming shallow trench isolation (STI) structures.
Shallow trench isolation (STI) has become the most common and important isolation technology for sub-quarter micron complimentary metal oxide semiconductor (CMOS) devices. The edge treatment of STI is one of the key issues to suppress the corner effects and to maintain gate oxide integrity. Issues such as edge leakage, inverse narrow channel effect and xe2x80x9chumpsxe2x80x9d in Id-Vg curves become critical as the isolation pitch is scaled down.
The conventional STI process flow includes pad oxide and chemical vapor deposition (CVD) silicon nitride (SiN) deposition, active area masking, nitride/oxide etching, silicon (Si) trench etching, liner oxidation, high density plasma (HDP) oxide filling, chemical mechanical polishing (CMP) polishing, and nitride and pad oxide removal.
Well known issues in conventional STI processes include corner rounding and divot formation (i.e. oxide recess) along STI edges. The divot at the edge of the STI is formed due to wet dip of pad oxide by an HF solution. Although the liner oxidation can round the corner of the STI edge, the degree of rounding may not be enough.
Several techniques have been developed to reduce the divot slightly by etching the edge of the nitride layer (referred to as xe2x80x9cpull-backxe2x80x9d) after the silicon trench formation (but before liner oxidation). The corner is then exposed and becomes more rounded and thicker by the oxide growth by the subsequent liner oxidation. Another technique adds a poly-buffer layer in between the pad oxide and nitride (referred to as poly-buffer STI) so that the corner can become more rounded during liner oxidation. The poly-buffer layer also can reduce the stress from the nitride to the substrate. The pull-back and poly-buffer techniques may even be combined to result in even greater enhanced performance of STIs.
U.S. Pat. No. 6,228,727 B1 to Lim et al. describes a process to form STIs with rounded corners using spacers and an etch.
U.S. Pat. No. 6,232,203 B1 to Huang describes a process to form STIs without divots.
U.S. Pat. No. 5,866,435 to Park, U.S. Pat. No. 5,674,775 to Ho et al., U.S. Pat. No. 6,174,785 B1 to Parekh et al. and U.S. Pat. No. 6,001,707 to Lin et al. describe related STI fabrication processes.
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of forming shallow trench isolation (STI) structures.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a silicon structure having a pad oxide layer formed thereover is provided. A hard mask layer is formed over the pad oxide layer. The hard mask layer and the pad oxide layer are patterned to form an opening exposing a portion of the silicon structure. The opening having exposed side walls. A spacer layer is formed over the patterned hard mask layer, the exposed side walls of the opening and lining the opening. The structure is subjected to an STI trench etching process to: (1) remove the spacer layer from over the patterned hard mask layer; form spacers over the side walls; (2) the spacers being formed in-situ from the spacer layer; and (3) etch an STI trench within the silicon structure wherein the spacers serve as masks during at least a portion of time in which the STI trench is formed. The STI trench having corners. Any remaining portion of the spacers are removed. A liner oxide is formed at least within the STI trench whereby the liner oxide has rounded corners proximate the STI trench corners. An STI fill layer is formed over the patterned hard mask layer and filling the liner oxide lined STI trench. The STI fill layer is planarized, stopping on the patterned hard mask layer. The patterned hard mask layer and the patterned pad oxide layer are removed to form a divot-free STI structure having rounded corners.